1. Field of the Invention
This invention relates to a semiconductor memory device having sense amplifiers for amplifying data held in a memory cell array. Particularly, this invention relates to a semiconductor memory device which employs N channel preceding sensing method for controlling operation of the sense amplifiers.
2. Related Art
In general DRAM, a configuration is employed in which minute potential of a memory cell is read out and amplified by a sense amplifier disposed corresponding to a bit line pair as a complementary pair. FIG. 7 is a diagram showing a circuit configuration of a primary part of a conventional DRAM. In the circuit configuration of FIG. 7, a plurality of bit line pairs BLT/BLN is arranged repeatedly, and a plurality of memory cells MC each formed at an intersection of bit line BLT or BLN and a word line, a plurality of sense amplifiers each connected between the bit lines BLT and BLN and a VDL generating circuit 11 for generating an array voltage VDL are shown. Although a circuit configuration corresponding to an arbitrary bit line pair BLT/BLN will be described below, the circuit configuration is common to each bit line pair BLT/BLN.
The memory cell MC includes an NMOS transistor and a capacitor. A bit line BLT or BLN is connected to one end of the NMOS transistor and a power supply VPLT is connected to one end of the capacitor. The sense amplifier 10 is composed of a pair of NMOS transistors TN1 and TN2 and a pair of PMOS transistors TP1 and TP2. Each source of the pair of NMOS transistors TN1 and TN2 is connected to a voltage supply line SAN, and each source of the pair of PMOS transistors TP1 and TP2 is connected to a voltage supply line SAP. Each of the NMOS transistor TN1 and the PMOS transistor TP1 has a drain connected to the bit line BLT and a gate connected to the bit line BLN. Each of the NMOS transistor TN2 and the PMOS transistor TP2 has a drain connected to the bit line BLN and a gate connected to the bit line BLT. By such connection, the minute potential difference generated between the bit lines BLT and BLN corresponding to accumulated charge of the memory cell MC is amplified by the sense amplifier 10.
The VDL generating circuit 11 is a circuit which generates the array voltage VDL necessary for operation of each sense amplifier 10. The array voltage VDL is connected to the voltage supply line SAP through a PMOS transistor TP3. The PMOS transistor TP3 turns ON in response to a control signal SEP applied to its gate and is activated when the array voltage VDL is supplied to the voltage supply line SAP. And a ground potential VSS is connected to the voltage supply line SAN through an NMOS transistor TN3. The NMOS transistor TN3 turns ON in response to a control signal SEN applied to its gate and is activated when the voltage supply line SAN is connected to the ground potential VSS.
The operation of the sense amplifier 10 of FIG. 7 depends on threshold voltages Vtn of the NMOS transistors TN1 and TN2 and threshold voltages Vtp of the PMOS transistors TP1 and TP2. Generally, due to manufacturing limitation, fluctuations occur in the threshold voltages Vtn of the NMOS transistors TN1 and TN2 and the threshold voltages Vtp of the PMOS transistors TP1 and TP2 in accordance with a certain probability distribution. In the circuit configuration of the sense amplifier 10, if an unbalance of fluctuations of the threshold voltages Vtn (referred to as Vtn unbalance) of the pair of the NMOS transistors TN1 and TN2 exists, or if an unbalance of fluctuations of the threshold voltages Vtp (referred to as Vtp unbalance) of the pair of the PMOS transistors TP1 and TP2 exists, then an offset of the sense amplifier 10 occurs. The offset of the sense amplifier 10 corresponds to a limit to which the minute potential difference of the bit line pair BLT/BLN can be amplified when starting the sensing. If the offset of the sense amplifier 10 is greater than the minute potential difference of the bit line pair BLT/BLN, the sensing of the sense amplifier 10 fails. Thus, it is desirable to reduce the offset of the sense amplifier 10 sufficiently.
FIG. 8 shows characteristics of fluctuations of the threshold voltages Vtn and Vtp in a general DRAM process. In FIG. 8, characteristic Cn indicating the above-mentioned Vtn unbalance and characteristic Cp indicating the above-mentioned Vtp unbalance are compared. In the characteristic Cn, differences between the threshold voltages Vtp of the NMOS transistors N1 and N2 are measured for a large number of the sense amplifiers 10 and frequencies of the measured values are plotted. In the characteristic Cp, differences between the threshold voltages Vtp of the PMOS transistors P1 and P2 are measured for a large number of the sense amplifiers 10 and frequencies of the measured values are plotted. Both characteristics C1 and C2 have characteristics based on a normal distribution.
Meanwhile, as shown clearly in FIG. 8, the Vtp unbalance of the characteristic Cp is greater than the Vtn unbalance of the characteristic Cn. In the circuit configuration of FIG. 7, the offset of the sense amplifier 10 is determined based on an internal division between the Vtn unbalance and the Vtp unbalance. Thus, when the voltage supply lines SAN and SAP are activated at the same timing, an influence of the Vtp unbalance is dominant regarding the offset of the sense amplifier 10. On the contrary, if the voltage supply line SAN is activated earlier when starting the sensing, the offset of the sense amplifier 10 can be reduced.
Therefore, in order to take measures against the offset of the sense amplifier 10, it is effective to employ N channel preceding sensing method in which the voltage supply line SAN is activated in the first place, and after the potential difference of the bit line pair BLT/BLN is increased, the voltage supply line SAP is activated (for example, see JP H08-235861).
FIG. 9 shows an example of operation waveform in a case where the N channel preceding sensing method is employed in the sense amplifier 10. As shown in FIG. 9, in a sensing operation for a memory cell MC to be accessed, a selected word line is activated at timing T1 and its voltage rises from the ground potential VSS to a voltage VPP. Thereby, a minute potential difference corresponding to the accumulated charge of the memory cell MC is generated between the bit lines BLT and BLN. In FIG. 9, a case is shown in which voltage levels of the bit line pair BLT/BLN are maintained at a pre-charge voltage VHB at timing T1 by an equalizing circuit (not shown), and the voltage level of one bit line BLT is slightly decreased by the activation of the word line.
At timing T2, the NMOS transistor TN3 is turned on by the control signal SEN to activate the voltage supply line SAN, and the potential difference of the bit line pair BLT/BLN gradually increases by the operation of the NMOS transistors TN1 and TN2. At this time, the voltage level of the voltage supply line SAN decreases via the NMOS transistor TN3, and clamped at a voltage level lower than the pre-charge voltage VHB by the threshold voltage Vtn. As shown in the circuit configuration of FIG. 7, the NMOS transistors TN1 of the sense amplifier 10 has a source biased at the voltage level of the voltage supply line SAN and a gate biased at the voltage level of the bit line BLN. Thus, when its gate-source voltage becomes greater than the threshold voltage Vtn, the NMOS transistor TN1 turns ON, leading to a state where capacitance of the bit line BLN is connected to the voltage supply line SAN. Thereby, the voltage level of the voltage supply line SAN hardly changes rapidly and thus the above-mentioned characteristics is achieved.
At timing T3, the NMOS transistor TP3 is turned on by the control signal SEP to activate the voltage supply line SAP, and the potential difference of the bit line pair BLT/BLN further increases by the operation of the PMOS transistors TP1 and TP2 as well as the NMOS transistors TN1 and TN2. At this time, the voltage level of the voltage supply line SAP increases via the PMOS transistor TP3, and changes from the pre-charge voltage VHB to the array voltage VDL. As time elapses, the voltage level of one bit line BLN converges to the array voltage VDL gradually and the voltage level of the other bit line BLT converges to the ground potential VSS gradually.
In this manner, since the activation of the voltage supply line SAN precedes that of the voltage supply line SAP, in the case where the potential difference between the bit lines BLT and BLN is small, the amplification operation is performed using the NMOS transistors TN1 and TN2 in which fluctuations of the threshold voltages Vtn are small, so that the influence of the offset of the sense amplifier 10 can be reduced.
However, in recent years, downsizing in the DRAM process is facilitated, and from viewpoints of reliability and reduction of consumption current, the lower array voltage VDL is required. If a configuration using the lower array voltage VDL is employed, there is a great influence on the operation of the sense amplifier 10 in which the N channel preceding sensing method is employed. FIG. 10 shows an example of operation waveform in a case where the array voltage VDL is lowered in comparison with FIG. 9.
In FIG. 10, the array voltage is lowered than that in FIG. 9 and accordingly the pre-charge voltage VHB is lowered. In the sensing operation, after the voltage of the word line rises at timing T1, the voltage supply line SAN is activated at timing T2, and the bit line BLT falls to a voltage level lower than the per-charge voltage VHB by the threshold voltage Vtn. At this time, since VHB-VSS is lower than the threshold voltage Vtn, it is difficult to increase the potential difference of the bit line pair BLT/BLN by the operation of the NMOS transistors TN1 and TN2. Thus, when the voltage supply line SAP is activated at timing T3, the potential difference of the bit line pair BLT/BLN is kept small, and an influence of the Vtp unbalance becomes dominant. As a result, the offset of the sense amplifier 10 increases, and thereby the possibility that the sensing may fail increases. This causes a problem that DRAM chips which cannot be rectified by redundancy cells and the yield thereof decreases.
Further, there is a method as a measure for the above-mentioned problem in which process of the NMOS transistors of sense amplifiers is separated from processes in other areas of DRAM so as to reduce the threshold voltage Vtn. However, this method brings about a problem of an increase in active standby current flowing in a state where the sense amplifiers are activated.